Noise reduction in a power converter

ABSTRACT

The present invention concerns a control device ( 28 ) for a switching power converter ( 10 ), a switching power converter and a method of controlling a switch in a power converter for reducing audible noise. The power converter comprises the control device ( 28 ) and at least one switch ( 26 ) for regulating the power conversion. The control device ( 28 ) comprises a timer ( 45 ) for monitoring a switching frequency of the switch ( 26 ) to indicate when the frequency has dropped to a certain level, and a gate driving circuit ( 32 ) connected to the timer and arranged to regulate the switching of the switch in dependence of the indication from the timer, so that the frequency rises above said certain level in order to reduce generation of audible noise.

TECHNICAL FIELD

The present invention relates to a control device for reducing audiblenoise, a power converter including such a control device as well as to amethod of controlling a power converter, such as in a quasi-resonantswitched mode power converter for use in TVs, VCRs, printers, computersetc.

BACKGROUND OF THE INVENTION

In many switched mode power converters the minimal frequency is notlimited below 20 kHz, like for instance in quasi-resonant converters.This means that the converter can generate audible noise, which is notacceptable and which can be perceived by the human ear. In someconverters like fly-back converters this can happen when the converteris short-circuited, at start up or when turning off the converter. Whena quasi-resonant power converter is driven at high power levels, thefrequency with which the converter is switched gets lower. The switchingfrequency is furthermore lowered when the current through the switchgets high, which switch is normally realized with some kind oftransistor circuit, like a FET transistor. There thus exists a problemwith the converters of today.

U.S. Pat. No. 6,011,361 describes a buck converter for igniting andoperating a high-pressure discharge lamp. Here the maximum off time ofthe transistor switching the converter can be set preventing operationsbelow 20 kHz. In this document there is no monitoring or directlimitation of the frequency, only limitations for the off time are set.These limitations are set all the time irrespective of if the switchingfrequency is high or low. The off time gets an upper limit of 36 μs anda lower limit of 5 μs. With regard to audible noise, the switch isturned on if a time limit for the off time is reached. In order for thisdevice to work for reducing audible noise, the load and the inputvoltage have to be known. Since the circuit is arranged for driving alamp, which load is known, this works well in this environment. It wouldhowever not work properly for a power supply for reducing audible noise,because a power supply has to be able to work with several differenttypes of loads and limitation of the switching period is only to be madewhen the frequency is actually low and not when the converter is workingnormally. The document does also not describe limiting of the peakcurrent in the transistor in a discontinuous conduction mode.

SUMMARY OF THE INVENTION

The present invention is directed towards the problem of reducingaudible noise in power converters, which can for example be present atstart up, short circuit, overpower or when turning off a converter. Theinvention is defined by the independent claims. The dependent claimsdefine advantageous embodiments.

The problem is solved by a method of controlling a power convertercomprising at least one switch, where the switching frequency of thefirst switch is monitored and the first switch is controlled so that thefrequency stays above a certain level generating audible noise.

With a preferred embodiment of the present invention there is realized aconverter which requires few extra components in the control device,which thereby keeps the cost of the control device and converter low.Additional benefits of the invention will be evident from the followingdescription

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a fly-back converter according to apreferred embodiment of the invention.

FIG. 2 shows the controller of a fly-back converter according to thepreferred embodiment of the invention.

FIG. 3 is a graph showing various currents and voltages during a fewcycles of operation of the converter of FIG. 1.

FIG. 4 is a graph showing various currents and voltages during anotherfew cycles of operation of the converter of FIG. 1.

FIG. 5 shows a schematic diagram of a fly-back converter according toanother embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will in the following be described in relation tofly-back converters for DC/DC conversion. The invention is however in noway limited to such converters or only to DC/DC conversion, but can beimplemented in any type of converter. Like for example buck, boost orbuck-boost. Conversion can likewise be other types of conversion likeAC/DC, DC/AC or AC/AC.

FIG. 1 shows a fly-back converter 10 according to the invention workingas a power supply. The shown converter is a converter where current modecontrol is used. In this converter there is an input voltage source 12having a voltage V_(IN), connected between ground and a first end of aprimary winding 16 of a power conversion means in the form of atransformer 14. The second end of the primary winding 16 is connected tothe drain of a first transistor or first switch 26, which transistor ispreferably a FET transistor. The gate of the first transistor 26 isconnected to a driver output 40 of a control device or controller 28.The source of the transistor 26 is connected to a sense resistor 44,which in turn is connected to ground. The connection point between thesource of the transistor 26 and the sense resistor 44 is connected to asense input 43 of the controller 28 via a parallel circuit comprising aresistor 46 and a capacitor 48. The controller 28 has a groundingterminal 42 connected to ground for grounding the different circuitsmaking up the controller. The controller 28 includes a power-on-resetcircuit 34 and an oscillator 36, both connected to a PWM controller orgate driving circuit 32. The gate driving circuit 32 is also connectedto a control input 38 and the sense input 43. The gate driving circuit32 is furthermore connected to a reset input R of a RS flip-flop 30 andto a set input S of the RS flip-flop 30. The RS flip-flop has an outputQ connected to the gate of the transistor 26. The controller 28 has atimer 45 connected between the driver output 40 and the gate drivingcircuit 32.

A first end of a secondary winding 18 of the transformer 14 is connectedto a diode 20, which in turn is connected to a first capacitor 22 and aload 24. The load 24, first capacitor 22 and second winding 18 of thetransformer 14 are also connected to ground, preferably via galvanicisolation. A connection point between the diode 20, the capacitor 22 andthe load 24 is also connected to the control input 38 of the controller28. The connection point is preferably connected to the control input 38via an optocoupler.

FIG. 2 shows an electric circuit diagram of parts of the controller 28according to a preferred embodiment of the present invention. The senseinput 43 of the controller 28 is connected to a first input of acomparing device in the form of a first comparator 52, which firstcomparator is provided in the gate driving circuit 32. A current source56 is connected to said first input of the comparator 52 via a secondswitch 54. A second input of the comparator 52 is connected to a voltagesource 50. The output of the first comparator 52, which output isconnected to the transistor 26 which forms a first switch, is alsoconnected to a clock input dk of a D flip-flop 58. A second comparator57 has an output connected to a D input of the D flip-flop 58. Thesecond comparator 57 has a positive input terminal, which receives asignal from the previously mentioned timer, and a negative inputterminal, which is connected to a reference voltage V_(ref). The secondswitch 54 is controlled by the gate driving circuit 32 in a way, whichwill be described later on in this description. It is also understoodthat the second switch, the current source, the voltage source, the Dflip-flop and the second comparator are also provided in the gatedriving circuit.

FIG. 3 shows different voltages and currents of the fly-back converterof FIGS. 1 and 2. At the top of FIG. 3 there is shown the variation ofthe voltage U_(d) over the drain of the transistor 26 over time as wellas the input voltage V_(i). Below this voltage is shown the drivingvoltage pulses V₄₀ generated by the gate driving circuit 32 to the gateof the transistor 26 for switching it. Below the driving pulses is shownthe current I₂₆ running through the transistor 26 and below the currentthrough the transistor is shown the output current I₁₈ of the converter.Under the output current I₁₈ is shown a voltage V₄₅ supplied from thetimer 45 to the second comparator 57 together with the reference voltagelevel V_(ref). Under the voltage V₄₅ supplied from the timer 45 is shownan output voltage V₅₇ from the second comparator 57, and under thisvoltage V₅₇ another voltage S₅₄ supplied by the D flip-flop to thesecond switch 54. FIG. 4 shows the same types of currents and voltagesas FIG. 3, but for higher loads, i.e. higher output currents, and whenthe frequency gets so low that audible noise is generated.

Under normal operation, i.e. when the frequency is above a levelgenerating audible noise, the converter supplies an output voltage tothe load in known fashion. The controlling of the first switch 26 isalso done in known fashion using current control by regulating the peakcurrent through the switch 26 and sensing when the voltage across thedrain of the transistor 26 is minimal or zero. Alternatively one cansense if there is a zero crossing of the voltage across the primarywinding 16 of the transformer 14 and add a delay, this mode of operationis known as a critical discontinuous or self-oscillation power supply(SOPS) mode. The peak current for which switching is to be made is setby the output voltage of the converter. From FIGS. 3 and 4 it can beseen that the frequency gets lower at higher power levels, i.e. when theconverter delivers more current. Furthermore the peak current getslarger when the on time of the transistor 26 is longer, which alsolowers the frequency. The secondary stroke time, i.e. the time when thecurrent is flowing through the output stage, is dependent on the outputvoltage V₁₈. When the output voltage drops the secondary stroke timeincreases, so the frequency decreases. In normal operation the converterwill work in a frequency region above 20 kHz. When, however, there is alarge load, such as when the converter is short-circuited, at start up,overpower or when turning off the converter, audible noise can begenerated, which is highly undesirable. How these low frequencies can bereduced will in the following be described more closely. A typicalcontroller is described in the data sheet TEA1507 by PhilipsSemiconductors, which is hereby incorporated by reference.

As mentioned earlier the output voltage V₁₈ of the converter iscontrolled by controlling the conduction time of current in the primarywinding 16, using the controller 28. This current is determined bymeasuring the voltage over the sense resistor 44. This voltage is fed tothe gate driving circuit 32, which adjusts the conduction time of thetransistor 26, typically a field effect transistor such as a BJT or aMOSFET, in response to the sensed current. In the preferred embodimentthis is done through comparing the voltage across the sense resistorwith the voltage from the voltage source 50 in the first comparator 52,which generates a high voltage level. The high voltage level then turnson the first switch 26. When the transistor 26 is turned off, themagnetic field in the transformer 14 collapses, and energy stored in themagnetic field is converted into a current in the secondary circuit thatcharges the first capacitor 22. During the primary stroke the drainsource voltage U_(d) is about 0, during the secondary strokeU_(d)=V_(i)+nV₁₈, where n is the ratio between primary winding 16 andsecondary winding 18.

Under normal operation of the controller 28 the first switch 26 isturned on when the voltage across the drain is getting close to zero.This voltage can be provided by sensing the voltage via a sense terminalin the middle of the primary winding of the transformer. It can also beprovided by a transformer having an extra sense winding, which thecontroller senses or by some other suitable means. The control of theswitch 26 is made according to self-oscillating mode control or criticaldiscontinuous mode control, which is well known within the art. Thevoltage of the voltage source does not have to be fixed, but is variedin dependence of the measured output voltage as received on the controlinput of the controller 28. All this is standard current control of aconverter.

If the time is too long, i.e. the frequency reaches a set level, like 20kHz at which time audible noise is generated, the timer 45 sends asignal to the gate driving circuit 32 for regulating the first switch26. The gate driving circuit 32 then controls the first switch 26 sothat the frequency again rises.

As described earlier the timer 45 of the control unit 28 monitors thefrequency of the first switch 26. It does this by counting the timesince the switch 26 was last switched on. If the time reaches a set timelimit corresponding to a selected frequency, which in the preferredembodiment is 20 kHz, the limit for generating audible noise (i.e. thetime is 50 μs), an indication is given to the gate driving circuit. Thisis done through the timer 45 supplying a voltage, which increases withtime, to the second comparator 57. If this voltage is larger than thereference voltage V_(ref), the second comparator 57 supplies a highvoltage level to the D flip-flop 58. The reference voltage is here setso that the level V_(ref) will be reached by the voltage from the timerwhen a time corresponding the period of the set frequency is reached.The D-flip-flop 58 then sets its output Q high, the next time it getsclocked. The gate driving circuit then closes the second switch 54 atthe same time as the first switch 26 is turned on. This is accomplishedby the fact that the output of the first comparator 52, which is drivingthe first switch 26, is also used as the clock signal for the Dflip-flop 58, which D flip-flop 58 then clocks out the high voltagelevel turning on the second switch. This makes the current source 56start loading the capacitor 48. As this is done the voltage across thecapacitor 43 is added to the voltage across the sense resistor 44, whichleads to the comparator 52 switching off the first switch 26 at a lowercurrent level. As this is done the frequency of the first switch 26 israised. When the first switch 26 is switched off the second switch 54 iskept on. The timer 45 is reset once the first switch 26 is switched onand starts counting again. If the problem with the low frequencyprevails, the timer will generate another indication, which will keepthe second switch 54 on. If however the frequency goes above said setlevel, the output of the timer 45 will not reach the voltage levelV_(ref) and the second comparator 57 will therefore generate a lowvoltage that is supplied to the D flip flop 58. The next time the Dflip-flop 58 gets clocked by the turning on of the first switch 26, theQ output of the D flip-flop goes low, which turns off the second switch54. The resistor 46 is used for unloading the capacitor 48.

With the preferred embodiment frequencies generating noise aresubstantially reduced. The described example was given for currentcontrol. The described preferred embodiment is a cost-effective method.The resistor 46 and capacitor 48 already exist in many systems for softstart up of the converter. This means that the invention is cheap sinceno extra components are needed. It is also a well-known fact that it isessential to keep the number of components in a converter at a minimumin order to keep down the costs. Since the resistor 46 and capacitor 48are not in the controller, they can be chosen at will in order to getgood operation of the invention. This gives great flexibility whendeciding how fast the peak current limitation is to be done. Thispreferred embodiment has also been tested with good results.

The invention is also possible to implement using voltage control. Avoltage-controlled converter is shown in FIG. 5. FIG. 5 is in many wayssimilar to FIG. 1. The difference is that the controller does not have asense input 43 and that there is no sense resistor 44 or parallelcircuit 46,48 in the converter of FIG. 5. The rest of the parts areidentical and will not be further described here. In this case the ontime of the first switch 26 is limited by direct PWM-control. Here theon time is controlled by the output voltage. Raising a voltage comparedwith a reference voltage can also here provide on-time limitation.Indication of low frequency can also here be provided using a comparatorconnected to the timer. However, current control is in many casespreferred to voltage control, since then the control is more direct andfaster.

There is one instance when there can be a frequency below 20 kHz,despite the above-mentioned control of the on time of the first switchaccording to the present invention. The first switch 26 has a minimal ontime, i.e. a smallest time it can be on. If the on time limitation setby gate driving circuit 32 is lower than this, the first switch 26cannot go under this limit. In this case the frequency can go below theset limit. However the noise cannot be heard in this case, because thenthe peak currents in the system are also low.

There is an alternative embodiment of the invention and that is that thefirst switch 26 is directly turned on once the indication is received.Once the gate driving circuit 32 receives the indication from the timerit then immediately turns on the first switch 26. This can beimplemented by suitable logic circuits given the teachings of thepreferred embodiment. The converter then enters continuous conductionmode and this directly limits the frequency. There is however oneproblem with this embodiment and that is that the diode 20 on the outputside might get hot.

In order to solve this the second embodiment of the invention can becombined with one of the previously described embodiments, i.e. that thefirst switch 26 is automatically switched on when the frequency goes toor under the set frequency level ad at the same time the on time of theswitch is also limited by either current control or voltage control.This decreases the temperature of the diode 20.

Finally a method of controlling a converter according to the inventionwill be described. In the described method the method of limiting the ontime of the first switch 26 by current control will be described withhow the first switch 26 is regulated and then how the second switch 54is regulated. The method is furthermore preferably implemented in formof hardware.

The method of controlling the first switch is started when the converteris turned on. Thereafter the switch is turned on. Then, there is acomparison between the added voltages, i.e. the voltages over thecapacitor 48 and the sense resistor 44, with the voltage V₅₀. If theadded voltages are above the voltage V₅₀, then the first switch 26 isturned off. If not the comparison is made again. It should be noted thatif there is no low frequency, then the voltage of the capacitor 48 iszero and the comparison is only made between the voltage across thesense resistor 44 and V₅₀, which is the normal mode of operation.Thereafter, it is investigated if there exists a signal for turning onof the first switch 26. In the preferred embodiment this is indicated bythe fact that a zero crossing of the voltage across the primary windingof the transformer is taking place. If there is no such indication orsignal, a new investigation is made. If however there is such anindication, the switch 26 is turned on again, and the method goes on aspreviously described as long as the converter is turned on.

The method of controlling the second switch 54 is likewise started whenthe converter is turned on. Then, it is investigated if there is arising edge of a gate-driving signal for turning the first switch 26 on.If there is such a signal the timer 45 starts working by checking thefrequency, if not then the method waits for a new rising edge.Thereafter the method goes on with checking the frequency of the firstswitch 26. If the frequency stays above a certain set level or does notgo below it, the second switch 54 is turned off if it was previouslyturned on, and it is again investigated if there is a rising edge of agate driving signal. If however the frequency is below the level, whichin the preferred embodiment is 20 kHz, an indication is made to thateffect. Then the second switch 54 is turned on if it was not alreadyturned on. By turning on the second switch 54 the capacitor 48 is loadedand the voltage of the capacitor 48 is added to the voltage across thesense resistor 44 for use in the comparing step of the regulation of thefirst switch 26. After this, investigation of a rising edge of thegate-driving signal is resumed. Thereafter the method continues asdescribed above.

If the invention is combined with going into continuous conduction modeand turning on the first switch 26 after the indication, then the stepof turning on the second switch 54 is provided with generation of asignal for turning on the first switch 26. If the invention is used onlywith putting the converter in continuous conduction mode, the steps ofturning off and on the second switch 54 are omitted, and there is noadding of voltages in the comparing step in the regulation of the firstswitch 26, i.e. only the voltage across the sense resistor 44 iscompared with V₅₀.

Preferred embodiments of this method can be summarized as follows.Method of controlling at least one first switch in a power convertercomprising the steps of monitoring the switching frequency of the firstswitch and controlling the first switch so that the frequency staysabove a certain level generating audible noise. Preferably, such amethod comprises the further step of indicating when the frequency fallsto said level. Preferably, the step of controlling includes turning onthe first switch automatically after the indication. Preferably, thestep of controlling includes limiting the on time of the first switch.Preferably, the on time is limited by direct PWM control. Preferably,the on time is limited by limiting the peak current running through thefirst switch. Preferably, the step of controlling includes adding avoltage to the voltage of a sense resistor through which current throughthe first switch is also running, and comparing the added voltages witha reference voltage for switching off the first switch. Preferably, theadding of a voltage is done by loading a capacitor with current from acurrent source. Preferably, the loading of current is started upon saidindication.

With the present invention audible noise from the converter is thusreduced. The present invention normally works when exceptionaloperational circumstances exist such as over power, short circuit, startup or turning off the converter. A simple, cheap and effective way ofreducing audible noise in a power converter has thus been explained. Itshould be noted that the above-mentioned embodiments illustrate ratherthan limit the invention, and that those skilled in the art will be ableto design many alternative embodiments without departing from the scopeof the appended claims. In the claims, any reference signs placedbetween parentheses shall not be construed as limiting the claim. Theword “comprising” does not exclude the presence of elements or stepsother than those listed in a claim. The word “a” or “an” preceding anelement does not exclude the presence of a plurality of such elements.The invention can be implemented by means of hardware comprising severaldistinct elements, and by means of a suitably programmed processor. Inthe device claim enumerating several means, several of these means canbe embodied by one and the same item of hardware. The mere fact thatcertain measures are recited in mutually different dependent claims doesnot indicate that a combination of these measures cannot be used toadvantage.

1. A control device (28; 28′) for a switching a power converter (10) forreducing audible noise, the power converter comprising at least oneswitch (26) for regulating a power conversion, the control devicecomprising: means (45) for monitoring a switching frequency of theswitch (26) to indicate when the switching frequency has dropped to acertain level, and means (32) for regulating switching of the switch(26) in dependence on the monitoring means (45), so that the frequencyrises above said certain level in order to reduce generation of audiblenoise.
 2. Control device according to claim 1, wherein the regulatingmeans (32) are arranged to directly turn on the switch (26) whenreceiving an indication from the monitoring means (45).
 3. Controldevice according to claim 1, wherein the regulating means (32) arearranged to limit the on time of the switch (26) when receiving anindication from the monitoring means (45).
 4. Control device accordingto claim 3, wherein the regulating means (32) are arranged to limit theon time by direct PWM control.
 5. Control device according to claim 3,wherein the regulating means (32) are arranged to limit the on time bylimiting a peak current running through the switch (26).
 6. Controldevice according to claim 5, further comprising a second switch (54) andmeans (52) for comparing a voltage corresponding to a current runningthrough the switch (26) with a reference voltage for turning the switch(26) on and off, wherein the regulating means (32) are arranged toswitch on the second switch (54) when the indication is received fromthe monitoring means (45), for adding a voltage to the voltagecorresponding to the current through the switch (26), in order to limitthe peak current running through the switch (26).
 7. Control deviceaccording to claim 6, further comprising a current source (56) connectedto the second switch (54), which second switch (54) is connectable to acapacitor (48), the capacitor being connectable to the comparing means(52) and connected to the source of the switch (26), to which source asense resistor (44) for sensing the current through the switch (26) isconnected, wherein the added voltages are made up of the voltage acrossthe capacitor (48) and the voltage across the sense resistor (44). 8.Control device according to claim 6, wherein the regulating means (32)are arranged to turn off the second switch (54) if the monitoring means(45) have not generated an indication the next time the switch (26) isturned on.
 9. A switching power converter, comprising: power conversionmeans (14), at least one switch (26) for regulating the power conversionmeans (14), means (45) for monitoring a switching frequency of theswitch (26) to indicate when the switching frequency has dropped to acertain level, and means (32) for regulating a switching of the switch(26) in dependence on the monitoring means (45), so that the frequencyrises above said certain level in order to reduce generation of audiblenoise in the converter.
 10. Method of controlling at least one switch(26) in a power converter, the method comprising the steps of:monitoring (45) a switching frequency of the switch (26); andcontrolling (32) the switch (26) so that the switching frequency staysabove a certain level generating audible noise.